As a dot matrix type display device, liquid crystal display devices are employed for various devices such as a personal computer, because of its advantages of thinness, light weight, and low power consumption. Among them, color liquid crystal devices with an active matrix system which are particularly advantageous for controlling image quality with high definition, have become mainstream. In the liquid crystal display device of this type, an output circuit provided with operational amplifiers of a voltage follower connection and a bias circuit for controlling the bias currents of the operational amplifiers is employed as the output circuit of a data side driving circuit formed of a semiconductor integrated circuit device, for driving a data line of a liquid crystal panel (LCD panel) that is a capacitive load.
An output circuit 101 shown in FIG. 7 is an output circuit of a two-amplifier system, and includes a plurality of push output type operational amplifiers 1 (of which only one is shown) for outputting rising waveforms and a plurality of pull output type operational amplifiers 2 (of which only one is shown) for outputting falling waveforms, as the operational amplifiers. A circuit example of an operational amplifier 1 is illustrated in FIG. 8, and a circuit example of an operational amplifier 2 is illustrated in FIG. 9 (refer to Patent Document 1, for example). The operational amplifier 1 has a terminal 3 for supplying (N-biasing) a bias voltage VbiasA to internal N-channel MOS transistors Q5 and Q7. The operational amplifier 2 includes a terminal 4 for supplying (P-biasing) a bias voltage VbiasB to internal P-channel MOS transistors Q15 and Q17. Further, a bias circuit 10 is provided as the bias circuit. From the bias circuit 10, the bias voltage VbiasA is supplied to the terminal 3 of the operational amplifier 1 through an N-bias line 11, and the bias voltage VbiasB is supplied to the terminal 4 of the operational amplifier 2 through a P-bias line 12.
An output circuit 102 shown in FIG. 10 is the output circuit of a one-amplifier system, and includes a plurality of push-pull output type operational amplifiers 5 (of which two are shown) each for outputting both rising and falling waveforms, as the operational amplifiers. A circuit example of an operational amplifier 5 is illustrated in FIG. 11 (refer to Patent Document 2, for example). The operational amplifier 5 includes a terminal 6 for supplying the bias voltage VbiasA to the internal N-channel MOS transistor Q5 and a terminal 7 for supplying the bias voltage VbiasB to the internal P-channel MOS transistor Q15 and the like. Further, as the bias circuit, a bias circuit 10 is provided, as in FIG. 7. From the bias circuit 10, the bias voltage VbiasA is supplied to the terminal 6 of the operational amplifier 5 through the N-bias line 11 and the bias voltage VbiasB is supplied to the terminal 7 of the operational amplifier 5 through the P-bias line 12.
Referring to the output circuits 101 and 102 described above, the ones provided with the bias circuit for controlling the bias currents of the operational amplifiers 1, 2, and 5 so as to improve the slew rates at the times of rise of the output signals of the operational amplifiers 1 and 5 and falls of the output signals of the operational amplifiers 2 and 5 as the bias circuit 10 are employed (refer to Patent Document 1, for example). A conventional bias circuit 20 will be described below with reference to FIG. 12. [Note, reference is made to JP-A-2003-66919, paragraph [0006] and its FIG. 10 which correspond to the FIG. 12 of the instant invention.] The bias circuit 20 includes a bias current source 21 and a bias voltage extracting circuit 22. The bias current source 21 includes an inverter 23 and P-channel MOS transistors Q21 and Q22 for the bias current source that are connected in parallel and have mutually different ON-resistances R1 and R2 (not shown), respectively, in which R1 is larger than R2. Sources of the MOS transistors Q21 and Q22 are connected to a high-voltage side terminal VDD, and drains of the MOS transistors Q21 and Q22 are connected to the bias voltage extracting circuit 22. The gate of the MOS transistor Q22 is connected in common to the gate of the MOS transistor Q21 via the inverter 23 and is connected to a bias switching terminal 9.
The bias voltage extracting circuit 22 includes N-channel MOS transistors Q23, Q24, and Q27 and P-channel MOS transistors Q25 and Q26. The N-channel MOS transistor Q23 is connected between the bias current source 21 and a low-voltage side terminal VSS. The N-channel MOS transistor Q24 is mirror connected to the MOS transistor Q23. The P-channel MOS transistor Q25 is connected in series with the MOS transistor Q24 between the high-voltage side terminal VDD and the low-voltage side terminal VSS. The P-channel MOS transistor Q26 is mirror-connection with to the MOS transistor Q25. The N-channel MOS transistor Q27 is connected in series with the MOS transistor Q26 between the high-voltage side terminal VDD and the low-voltage side terminal VSS. The drain of the MOS transistor Q23 is connected to the drains of the MOS transistors Q21 and Q22. The source of the MOS transistor Q23 is connected to the low-voltage side terminal VSS, and the MOS transistor Q23 has the drain thereof and the gate thereof short-circuited for a diode connection. The drain of the MOS transistor Q24 is connected to the drain of the MOS transistor Q25, the source of the MOS transistor Q24 is connected to the low-voltage side terminal VSS, and the gate of the MOS transistor Q24 is connected to the gate of the MOS transistor Q23. The source of the MOS transistor Q25 is connected to the high-voltage side terminal VDD, and the MOS transistor Q25 has the drain thereof and the gate thereof short-circuited for the diode connection. The source of the MOS transistor Q26 is connected to the high-voltage side terminal VDD, the drain of the MOS transistor Q26 is connected to the drain of the MOS transistor Q27, and the gate of the MOS transistor Q26 is connected to the gate of the MOS transistor Q25. The source of the MOS transistor Q27 is connected to the low-voltage side terminal VSS, and the MOS transistor Q27 has the drain thereof and the gate thereof short-circuited for the diode connection. Then, the series connection node between the MOS transistor Q26 and the MOS transistor Q27 is connected to the N-bias line 11 as the output terminal of the bias voltage VbiasA, and the series connection node between the MOS transistor Q24 and the MOS transistor Q25 is connected to the P-bias line 12 as the output terminal of the bias voltage VbiasB.
Next, an operation of the above-mentioned bias circuit 20 will be described. When a bias switching signal BIC at an “L (low) level” is supplied to the bias switching terminal 9, the MOS transistor Q21 is turned on. Then, the resistance of the bias current source 21 becomes the ON-resistance R1 of the MOS transistor Q21 (which is larger than R2 of Q22). Thus, a current corresponding to the ON-resistance R1 and smaller than that in a case associated with the ON-resistance R2 flows through the bias current source 21. Then, from the bias voltage extracting circuit 22, a bias voltage (being closer to VDD) smaller than that in the case associated with the ON-resistance R2 is supplied to the P-bias line 12, and a bias voltage (being closer to VSS) smaller than that in the case associated with the ON-resistance R2 is supplied to the N-bias line 11. When the bias switching signal BIC at a “H (high) level” is supplied to the bias switching terminal 9, the MOS transistor Q22 is turned ON, so that the resistance of the bias current source 21 becomes the ON-resistance R2 of the MOS transistor Q22 (which is smaller than R1). Thus, a current corresponding to the ON-resistance R2 and is larger than that in a case associated with the ON-resistance R1 flows through the bias current source 21. Then, from the bias voltage extracting circuit 22, a bias voltage larger (being farther from VDD) than that in the case associated with the ON-resistance R1 is supplied to the P-bias line 12, and a bias voltage (being farther from VSS) larger than that in the case associated with the ON-resistance R1 is supplied to the N-bias line 11.
The bias currents of the operational amplifiers 1, 2, and 5 are controlled by the bias circuit 20 as follows, thereby improving the slew rates at the times of rise of the output signals from the operational amplifiers 1 and 5 and fall of the output signals from the operational amplifiers 2 and 5. That is, at the times of the rise of the output signals from the operational amplifiers 1 and 5 and the fall of the output signals from the operational amplifiers 2 and 5, the bias switching signal BIC at the “H (high) level” is supplied to the bias switching terminal 9. The bias currents of the operational amplifiers 1, 2, and 5 are thereby set to be high by the bias circuit 20, so that the slopes of the rising waveforms of the output signals of the operational amplifiers 1 and 5 and the slopes of the falling waveforms of the output signals of the operational amplifiers 2 and 5 become sharp. During predetermined periods before and after the rise of the output signals of the operational amplifiers 1 and 5 and the fall of the output signals of the operational amplifiers 2 and 5, the bias switching signal BIC at the “L (low) level” is supplied to the bias switching terminal 9. The bias currents of the operational amplifiers 1, 2, and 5 are thereby set to be low by the bias circuit 20. Thus, during the periods, electric current consumption of the operational amplifiers 1, 2, and 5 is reduced.    [Patent Document 1] JP Patent Kokai JP-A-2003-66919    [Patent Document 2] JP Patent Kokai JP-A-9-93055
The entire disclosure of these documents are incorporated herein by reference thereto.